A Complementary Metal Oxide Semiconductor (CMOS) device is a Metal Oxide Semiconductor (MOS) device in which transistors are arranged in a pairwise manner, each pair (MOSFET pair) including a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an N-type MOSFET. The P-type MOSFET (PMOSFET) and the N-type MOSFET (NMOSFET) of each pair are connected so that the PMOSFET is on (conductive) when the NMOSFET is off (non-conductive) and vice versa. A CMOS device may include a large number of MOSFET pairs and, in addition, further electronic devices such as resistors, capacitors, diodes, inductors, as well as unpaired NMOSFETs or PMOSFETs.
Delay dispersion in a transistor-based clock tree can be minimized and delays can be balanced by suitably dimensioning the various transistors in each branch of the clock tree. In one approach, the active areas of the transistors are dimensioned individually, generally resulting in differently sized MOSFET pairs on the CMOS device. For example, adjacent MOSFET pairs may be geometrically different from each other. For instance, one of the two MOSFET pairs may have larger transistor areas than the other one.
In many CMOS devices, P-type field effect transistors are embedded in an N-type region of the substrate whereas N-type field effect transistors are embedded in a P-type region. When the CMOS device is implemented using a P-type substrate, the N-type region can be implemented by producing an N-type well (N-well) in the substrate, e.g., by negative doping. When an N-type substrate is used, a P-type well (P-well) can be produced, e.g., by positive doping.
The PMOSFET and the NMOSFET of a MOSFET pair can be located near each other on opposite sides of the boundary between the P-type region and the N-type region (PN-boundary). It is often desirable to ensure that there is a certain optimal distance between a transistor and the PN-boundary, for instance in order to reduce a spurious effect known as the Well Proximity Effect (WPE). This desire can be in conflict with the aim of making the CMOS device as small as possible.
A layout of a semiconductor device is a description of the semiconductor device on a computer. A layout, or a more detailed description derived from it, can be used as input data in a chip fabrication process to fabricate the semiconductor device represented by the layout. Layouts are developed by integrated circuit designers using dedicated development tools. Many such development tools are based on standard cells. A standard cell is a representation of a limited region, typically a quad-shaped region, and it may include a plurality of subregions such as doped and undoped regions, metal regions and polysilicon regions, for example. The semiconductor device can be specified to a certain degree of detail in terms of a plurality of abutting standard cells. The standard cells are usually arranged in accordance with an orthogonal lattice.
It is an object of the invention to reduce well proximity effects without increasing the size of the device, especially when there are adjacent MOSFET pairs with different dimensions. It is another object of the invention to provide a method of designing a CMOS device with reduced well proximity effects and with good use of the die area using standard cells. It is a further object of the invention to provide a method for generating a layout of a CMOS device that is to be operated at different operating points.